Agnisys tools have a remarkable set of enhancements. The major new enhancements include plugin environment support in IDS-NG™, expression support in the soft reset, integration of 3rd party RTL in IDS-aggregation logic, and inserting delays/stages in bus read-write.
Once the register specification is captured, designers work on creating a synthesizable application logic layer for the intended functionality using addressable hardware registers. There is a need to create an automation technique to overcome the manual work of creating Application Logic with the help of the Complete-IP solution.Read More
In a digital system, reset is an action to clear any pending process and brings a system to normal condition or an initial state, usually in a controlled manner. The IDS property ‘resetsignal’ is used to add soft reset conditions in the RTL to reset any existing process on a hardware input signal. The property can also be used by combining all the reset signal properties with corresponding default values.Read More
IDS-generated assignments to prdata, pready, and pslverr do not contain the muxing of active slave selection logic, and generated aggregation logic has *pready as ANDed logic w.r.t the pready signal of the IDS generated blocks where it is assumed to be always ready to be accessed. Whenever aggregation logic selects a block, it will reduce its offset from the paddr before aggregation. The top component property “aggregation_logic = third_party”, can be used on the chip element to get an aggregator which contains the signals assignment with the active slave selection logic.Read More
IDesignSpec™ supports properties like wr_stb_stages and addr_decode_stages at the block/register level that gives the flexibility of adding/inserting delays in the read-back path and address decode logic in the generated RTL. With the delays added in the write strobe stages along with address decode logic the data received is held at the original clock tick until the delayed clock cycle when the address is finally decoded. Read More