In the first quarter of 2023, Agnisys delivered a significant collection of enhancements for the IDesignSpec suite.
Below, find some of the key enhancements in IDesignSpec Solutions Suite.
Unaligned decoding for high-level register address bits
Tunable flow addition in HTML
Support for constructing arrays of instances in Verilog, and
In version 126.96.36.199 of IDesignSpec, unaligned register decoding is supported. This allows high-level address bits to be generated in order to decode unaligned registers. Because it enables HDL designers to decode register addresses using only the minimal LSB address bit, reliance on area intensive comparators is lessened. Consequently, designers can more quickly and affordably decode register addresses in their designs.Read More
IDesignSpec has three properties – treset, tdesc, and tphase – that allows users to change the register default reset value without affecting the functionality or physical characteristics of the hardware during post-silicon validation. These adjustable attributes can be presented in the HTML output for user reference.Read More
A new feature in IDS-Integrate now allows users to add instances of a block in a parent block using an API soc_add. Users can add multiple instances of the same block in a parent block by using multiple soc_add API in the Tcl/Python script.Read More
IDS has a useful new feature that allows users to apply the "doc_repeat_compact" property to descendant chips or blocks to create a single HTML file for all repeat instances of the same component. Users can reduce the amount of time and memory used for generation by applying this property to instances that are repeated. All bloated instances can be inspected with the use of repeat indices, with users being routed to the same file for each repeat occurrence. The individual names and addresses appear when any index is clicked. Read More