This newsletter will give you a brief idea of various enhancements which have been made in Agnisys Tools and products. This will focus on Board Prototyping, Field Error Signals, Traceability in IDesignSpec and Verification Constructs in SystemRDL 2.0.
It is an established practice for most hardware engineers designing printed circuit boards (PCBs) to create a prototype board prior to full-scale manufacturing of boards for end products. Prototypes are typically developed to test proof-of-concept of single functions, before production of the finished product. One must however note that prototypes fall into several categories. Read more.
Field Error Signals
Error signals are part of the communication between a processor and an IP and play a vital role during design and verification stages. They enable the processor to be kept informed about any invalid access of a register/field, which may further result in transaction failure.
Traceability in IDesignSpecTM
It is often difficult to trace various outputs, for different components. Usually, in a specification, which contains thousands of registers, sub-blocks, or IPs, a mechanism like traceability would be of great help. It enables designers to trace the effect of any component in different outputs.
Verification Constructs in SystemRDL 2.0
SystemRDL is a textual representation of hardware-software interface comprising of addressable registers, interrupts, counters etc. The latest version of SystemRDL – version 2.0 was released in 2018 and includes new verification constructs, parameterization, data types etc. to name a few.