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Newsletter 2019 Q3 | Agnisys

In this newsletter, you will find thoughts and insights about SystemRDL loopholes, security design strategies in IDesignSpec, RISC-V TileLink Bus Protocol Support in IDesignSpec, and Hierarchical Decode.


Thoughts and Insights on SystemRDL Loopholes

The Accellera SystemRDL supports the full project cycle of registers from the specification, model generation, and design verification to maintenance and documentation, and minimizes the problems encountered in describing and managing registers. Typically, the system architect or hardware designer creates a functional specification of the registers in a design. Read more.

Security Design Strategies in IDesignSpec

Security is one of the most important aspect of SoCs/IPs in the Internet-of-Things (IoT) era. Securing your SoCs/IP is critical for providing authentication, confidentiality, integrity, non-reproduction and access control to the system. Read More.

RISC-V TileLink Bus Protocol Support in IDesignSpec

New generation SoCs in deep learning applications require new types of processor architecture, and the open-source RISC-V ISA is picking up a lot of steam. As we know, Moore’s Law has ended and standard CPUs are not able to meet the performance and power requirements of new generation SoCs.  Read more.

Hierarchical Decode

Address decoding makes the memory or register function at a unique section/partition of the memory/register map. Without an address decoder, only one IP block can be connected to a processor, which would not be useful for today’s SoCs. For each IP Block, addresses can be decoded in two ways. Read More.