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Newsletter 2019 Q1 | Agnisys

In this newsletter, you will find articles about the basic differences between IP-XACT and SystemRDL, best practices on how to manage top-level designs, creating top-level register verification for SoCs and how to speed-up the UVM register model.


IP-XACT vs SystemRDL: Construct Comparison for Registers

Since its first release in 2010 by the SPIRIT consortium (now Accellera), IP-XACT has become the de-facto format for structuring, packaging, integrating and reusing IPs within tool flows.  One of the key reasons for its wide-adoption is its XML-based vendor-neutral format favorable to IP suppliers. IP-XACT can also describe components for memory and register maps, but quite limited in this area, especially as new types of register designs are needed to meet new requirements of next-generation SoCs. Read More


Creating Top-Level Registers Specification for an SoC

An SoC is a highly-integrated circuit that typically contains multiple sub-systems that consist of CPUs, GPUs, Memory, Wi-Fi and Display Controllers. When it comes to design and verification of SoC registers and memory maps, one of the best-practices in IDesignSpec is to employ a hierarchical approach in defining the SoC sub-systems and components as Board, Chip, Blocks, and Sub-blocks. This saves a lot of time and helps avoid many headaches during verification. Read More


How to speed-up the UVM register model 

While working on small separate block-level verification environments, it is easy to manage any performance issues that originate from the UVM register model. However, when validating a large SoC the UVM register model code can have a huge performance load, and can often become the bottleneck during system-level simulations. Read More


Efficiently Manage Multiple Top-Level Designs with Aggregation Logic 

Today’s electronics consumers demand more and more peripherals within their devices – that’s really good for the consumers, but problematic for SoC design and verification teams. The increasing number of peripherals entails a large number of internal I/O ports within the SoC which presents painful challenges in managing multiple top-level designs. It also entails changes in the working fully-scripted flow which consequently results in more bugs that need to be mitigated prior to tape-out. Read More