lp header

Webinar: IDesignSpec GDI for Safety-Critical Designs

In this webinar we discussed how the IDesignSpec GDI FS tool helps teams to develop Functionally Safe designs.

We hope you enjoy the webinar.


eBook: How Agnisys Eliminates Redundancies in Semiconductor Design, Verification, and Validation

Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Such a solution is available today.


Recent Blog Articles

November 28, 2023

Custom IP Design and AI-Based Verification

Experience the prowess of custom IP design and AI verification through Agnisys' IDS-IPGen. Streamline your chip development for optimal results.

IP-XACT usage in a SoC Design
November 22, 2023

Role of IP-XACT Standards for Efficient Manufacturing of IPs and SoCs

Agnisys optimises IP and SoC projects by using IP-XACT Standards, enhanced performance, and automating processes with advantageous sleek design.

VeeR EL2 Core Complex
October 31, 2023

How to Create Test Sequences for RISC-V Cores and SoCs Automatically

Learn how to efficiently create RISC-V core test sequences using IDesignSpec, streamlining development for data-centric computing adopted by numerous companies.


Request a Product Evaluation