Various new enhancements have been introduced recently in products like IDesignSpec™ (IDS) and ASVV™. A significant new enhancement to IDS has been chip-in-chip, now the chip can be a container for other chip hierarchies in addition to the block hierarchies that will ease the sub-system development.
IDS also supports different bus protocols for high performance data transfer among the Intellectual Property (IP) cores. The protocols like AMBA-AHB, AMBA-AXI, AMBA-APB, AVALON, I2C, SPI, TileLink or proprietary buses differentiate on features such as pipelining and burst. Each bus protocol has a widget. These widgets convert bus protocols into an internal bus (custom bus) for accessing the registers. Some bus protocols have different flavors and versions based on functionalities. Different versions of these widgets can be dynamically generated in the output according to the bus protocol used in the RTL.
Besides this, another enhancement for the use of SystemVerilog structures has been done. As it is evident for the simplicity in maintenance of RTL, aggregation of all the signals between multiple modules is done at one place. This could be done either with the use of structures or interfaces. Along with interfaces, IDS also supports SystemVerilog structures. It is capable of generating structures at the addrmap level to bundle ports coming out of the generated RTL. Moreover, a register in an IP block can now be typically accessed from two interfaces, one the cpu/software side, i.e., the standard bus protocol like AMBA-AHB, AMBA-AXI, etc., and the other the hardware side which has some signals that are connected with the application logic or some sensor interface.
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Testing Volatile Registers: A register in an IP block can typically be accessed from two interfaces, one from the cpu/software side i.e. the standard bus protocol like AMBA-AHB, AMBA-AXI, etc., and the other from the hardware side which has some signals that are connected with the application logic or some sensor interface. Read More
Use of SystemVerilog Structures instead of Interface: In SystemVerilog, hierarchical modules can be connected by simple data types, complex data types (structs, unions, etc.), or interfaces. The aggregating of all the signals between two modules in one place which simplifies maintenance of the code could be done using IDesignSpec™. Read More
Parameterization of Widgets: IDesignSpec™ supports different bus protocols for high performance data transfer among the Intellectual Property (IP) cores. The protocols like AMBA-AHB, AMBA-AXI, AMBA-APB, AVALON, I2C, SPI, TileLink, OCP or proprietary buses differentiate on features such as pipelining and burst. Read More
Chip-Inside-Chip Flow: IDesignSpec™ supports multiple design hierarchies like “block”, “chip”, “board”, and “system” to enable different architectural design flows. These act as a hierarchy of containers. A block can contain registers. A chip can contain other blocks and provide an aggregator for the blocks. A board is a container for multiple chips and similar to a chip in the generated outputs. Read More
