Various new enhancements have been introduced recently in IDesignSpec™(IDS). A significant new enhancement to IDS has been the introduction of SRAM based register implementation. IDS is capable of handling both dynamic and static registers. Dynamic registers are mapped to IDS internal registers while the static registers are mapped to memories.
Moreover, advanced quality checks have been introduced in IDS based on years of experience with all sorts of register maps. The checks ensure that all stages of the design development cycle are smooth, with shorter and efficient development time, and that the created optimum quality designs are efficient and reusable with no or fewer re-spins due to functional defects or problems.
IDS is also capable of generating Markdown output that reflects the test case in a formatted text file and support in the Markdown viewer. Markdown is a great tool for easily making formatted text files that display across a variety of platforms. Its innate flexibility and potential for use in a wide variety of contexts makes it a very useful output.
Besides this, the ‘next’ property can now accept an expression in the form of strings as its value in a defined register field or even in the field of any specific component among an array of parent/ancestor components to have software events that would act as conditions to update the next value in a field with respect to the value assigned to the property.
As always, your comments and suggestions are welcome.
Dynamic ‘Next’ Input Assignment With Events – IDesignSpec™ (IDS) has grown in terms of capacity and performance over the years. With new added features and enhancements in existing flow keeping backward compatibility intact, it has matured and diversified further in terms of functionality support. Read more
Markdown Output -Markdown is a lightweight markup language for creating formatted text using a plain-text editor. IDesignSpec™ is capable of generating Markdown output that reflects the test case in a formatted text file and support in the Markdown viewer. Read more
Quality Checks For Register Maps – Capturing registers is one of the most tedious and error-prone aspects of designing and implementing an SoC. In the absence of an automated solution, the effort involved in defining a register map grows exponentially, resulting in an increased cost and reduced time to market for the final product. Read more
SRAM based register implementation- In chips, register bits account for about 10% of the total standard cell area. This is expected to grow multiple fold for next generation chips, so we need to explore alternative methods of register implementation. Read more