SLIP-G™ – In any System-on-Chip (SoC) design there are certain standard IPs that are nearly ubiquitous and are used across many designs. A designer, generally, has two alternatives – either to spend time creating these IPs from scratch to meet their custom requirements or get them off-the-shelf.

Standard Library of IP Generators (SLIP-G) from Agnisys offers configurable standard IP generators as an extension to its addressable register generator tool. These IPs are designed to be easily customizable and configurable to meet any SoC requirements.

Agnisys provides IPs such as GPIO, TIMER, I2C Master, and PIC, which can also be configured and customized as per the user’s need. These IPs appear in a drop-down menu on the IDesignSpec ribbon or on IDS NextGen (IDS-NG).

IPs on IDS ribbon (IDSWord)

IPs on IDS-NG IDE

Its features are:

  • Highly customizable and configurable
  • Supports all IDS standard bus interfaces
  • Hooks to custom glue logic
  • Comes with standard APIs
  • Tested, verified, and validated IPs

In addition to the register specification for IPs, a set of standard programming sequences can be created for the IPs. These configuration sequences will help configure the IPs through a few arguments. The following table shows the APIs that are automatically generated for various IPs:

Standard IP API
GPIO •      GPIO_init_out_ext_src (out_pin , ext_src_sel)
•      GPIO_init_out_no_ext_src (out_pin , gpio_out_val)
•      GPIO_init_in_enb_posedge_detect (inp_pin , intr_enb)
•      GPIO_init_in_enb_negedge_detect (inp_pin , intr_enb)
•      GPIO_init_in_enb_pos_neg_edge (inp_pin , intr_enb)
TIMER •      reset_seq
•      timer_init_gen_seq (timer_en,timer_mode,timer_event_sel,timer_src_sel,timer_prescal)
•      running_mode_high_event (timer_src_sel, timer_prescal)
•      running_mode_low_event (timer_src_sel, timer_prescal)
•      running_mode_two_high_event (timer_src_sel, timer_prescal)
•      running_mode_two_low_event (timer_src_sel, timer_prescal)
•      periodic_mode_posedges_event
•      periodic_mode_negedges_event
•      periodic_mode_bothedges_event
•      default_event
PIC •      pic_vectored_negedge
•      pic_vectored_posedge
•      pic_vectored_level_low
•      pic_vectored_level_high
•      pic_non_vectored_level_low
•      pic_non_vectored_level_high
•      pic_non_vectored_posedge
•      pic_non_vectored_negedge
I2C •      i2cReset
•      i2cwrite (slave_addr , reg_addr , data_write , wr_intr_enb)
•      i2cread (slave_addr, reg_addr)

SLIP-G is a new, advanced, and better way of creating customizable and configurable designs.

Agnisys is also working on to develop new IPs in SLIP-G, such as SPI, UART, PWM, and DMA.