DVinsight™ is a smart editor for creation of Universal Verification Methodology (UVM) based System Verilog (SV) Design Verification (DV) code.
DVinsight™ is a design verification editor checker that provides helpful insight into user code and ensures compliance with UVM best practices while adhering to established standards. It helps to accelerate the learning curve of new DV engineers while accelerating error-free code development by the expert DV developer.
Key Features and Capabilities - Helpful on-the-fly checks and guides for creating SV/UVM code
Automatic compliance with the best-practice UVM guidelines
Fast and flexible navigation through the verification source code
The best-practice UVM guidelines are based on years of practical experience
Light-weight tool that enhances code creation productivity
Maintain current context using inline editing
Auto code completion
Context based hints
VIM and Emacs modes for fast adoption
Automatic code completion
Key Benefits – Faster adoption and cleaner SV/UVM code
Less errors, especially those that are not diagnosed by the SV/UVM compiler
Higher productivity and more thorough DV code
Faster adoption of System Verilog Universal Verification Methodology
Design Verification Editor Checker for any user experience level
DVinsight-Pro Pricing & Availability
DVinsight-Pro is available as a standalone tool following the “Freemium” pricing model. This means that the standalone tool is available at no cost to the users. The Freemium version of DVinsight-Pro will receive updates at Agnisys discretion up to two times per year.
Users may purchase a DVinsight-Pro maintenance services agreement for $4,995 per year for 50 users. Users with a maintenance agreement receive the most recent version of DVinsight-Pro and all updates throughout the year as they become available and have access to email support.
DVinsightPro is available on the following platforms:
- Redhat 7
- Redhat 6
- Redhat 5
- Windows (32 and 64 bit)