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We invite you to join us at DAC 2022 at the Agnisys Booth #2512, where we show the latest in automated IP and SoC Development.

  •  How do you achieve a lot with a small Design & Verification team?
  • Discover ways to make the automation work for you.
  • Find out the latest in making the specification become the golden source that drives the code development and tests.

Come and see why has become so popular. It is the Next Generation AI powered tool to convert English to SystemVerilog Assertions, from SystemVerilog Assertions to English, and from English spec to programming and configuration sequences.

We will be showing our latest innovation – The Complete-IP generation from specification. It’s an automation technique that generates the complete IP. Historically, teams have been content with generating the registers and bus interfaces from a register specification. Now we take the teams beyond that and save even more time.

We are also proud to announce that Agnisys software products and development flow has now received the much coveted ISO 26262 certification for any ASIL and is suitable to be used in safety-related development according to IEC 61508. Check our poster presentation titled “Automation of Functional Safety and Security Methods for Design and Verification”.

Find more details here,

Agnisys offers IDesignSpec(IDS) through which addressable register information can be captured for hardware specifications. IDS enables IP, SoC, and FPGA teams to standardize register specification and generate Verilog, VHDL, UVM, C headers, Word, Excel, PDF, and many other formats from it.

Once the register specification is captured, the next step is to create a synthesizable application logic layer for the intended functionality using these addressable hardware registers which require various design constructs. Manual effort in this case will be error-prone and often requires changes.

Therefore, there is a need to create an automation technique to overcome manual work of creating Application Logic. IDS will help in capturing the Register information as well as the Design functionality (Application Logic) with the help of a template based approach, which will help in the overall “Completeness” of an IP.

Verification using AI
AI based verification has become the holy grail of the current DV engineering community. Reducing or eliminating the need for verification will provide immense benefit to the design process even if it can be done in a certain limited scope.

What we bring to the table is our current state of experiment and development to describe how we can handle this area of verification using Artificial Intelligence (AI) and eliminate the monotonous chunks of this task. This novel approach works in IP/SoC settings with automated specification-based space to create correct by construction design code and then automatically verify them using AI. The focus is on using AI to maximize coverage by exploring its relationship with the verification constraints as well as its relationship with optimized tests created to hit appropriate design intents.

This in turn is expected to ease the tedious and time-consuming efforts involved to achieve verification results thus saving time and labor resources and reducing the time to market. was launched by Agnisys in Sep 2021 as a research and development effort to convert natural language into SystemVerilog Assertions (SVA). It’s a crowdsourced project where everyone can access and try out the system. At DAC, visitors can use the site to answer the quiz questions and win valuable prizes, and at the same time experience the power of AI.

ISO26262 and IEC 61508 Qualification for Entire SoC

Agnisys delivers a complete automated flow from register, sequence, and connection specification to assembly, design, verification, and validation of intellectual property (IP) and complex system-on-chip (SoC) devices using application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA) silicon technology. Many designs using the Agnisys solution are targeted for safety-critical applications, including automobiles and other vehicles. Systems designers insist that their silicon suppliers meet the ISO 26262 standard, which includes evaluating the tools used in the development flow.

We are proud to announce that Agnisys software products and development flow has now received the much coveted ISO 26262 certification for any ASIL and is suitable to be used in safety-related development according to IEC 61508. This means that now you can target safety-critical designs with IDesignSpec with complete confidence. At the DAC show, be sure to ask about the IDS 8 FS package.

Engagement formats

Booth Details:
Monday, July 11, 10:00 AM – 06:00 pm PDT
Tuesday, July 12, 10:00 AM – 06:00 pm PDT
Wednesday, July 13, 10:00 AM – 06:00 pm PDT

Schedule a Meeting at our Booth

Meet Agnisys at Booth number #2512

Poster Presentation
Automation of Functional Safety and Security Methods for Design and Verification

Time:06:00 PM –  07:00 PM PDT  Location:- Level 2 lobby

Description: Shift in the automotive industry towards automatic features, such as automatic gears, emergency braking to the craze of self-driven cars, there is a need to maintain fine precision. Automation has been done for writing specifications for such SoC to cater these growing needs. Complex issues are addressed with the help of various methods such as CRC, Parity, Sniffing Engine, SECDED and TMR. To ensure reliability and security of the code methods such as lock functionality, AES, Bus protection, HMAC and hardware Obfuscation have also been designed. All techniques have been automated to generate the RTL design and UVM model for SoC

Schedule A Demo

While you are at the booth, participate in the quiz and get a chance to win a Portable Projector. We will be choosing a winner every day. If you score more than 8 you can directly win a 30000mAh Power Bank.

Agnisys DAC Winning Prize

By NO Comment July 10, 2022

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