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Design Automation Conference (DAC) 2021

We invite you to join us at DAC 2021 at the Agnisys Booth #2516, where we show the latest in automated IP and SoC Development.

Come and see why everyone is talking about IDS-NG™, the Next Generation AI powered tool for IP/SoC design, verification, validation right from specification.


FPGA designers are faced with challenges of complex designs in addition to time-to-market pressures. Anything that can be done to speed up development while maintaining quality is highly desired. With Agnisys’ decade-long experience in Specification Driven Development it is uniquely poised to specifically target FPGA designs. With IDS-FPGA, teams can cut the development time in half using automated code generation, IP generators, and smooth integration with the target FPGA vendor software. Currently Xilinx and Intel FPGAs are supported.

At DAC, Agnisys will be showing a demo of this new product. Visitors will be able to see and appreciate the ease of use and automation to go directly from register and sequence specification to design and verification code.

 FPGA Specific features:

  1. Xilinx UltraScale+ IP based design development
  2. Integration with Vivado and Quartus
  3. Pre-captured ready-to-use IP library for target FPGA designs was launched by Agnisys in Sep 2021 as a research and development effort to convert natural language into SystemVerilog Assertions (SVA). It’s a crowd sourced project where everyone can access and try out the system. At DAC, visitors can use the site to answer quiz questions and win valuable prizes, and at the same time experience the power of AI.

Event Details: Schedule Meeting
Monday, December 6
10:00am – 6:00pm PST

Tuesday, December 7
10:00am – 6:00pm PST

Wednesday, December 8
10:00am – 6:00pm PST

Schedule a Demo

While you are at the booth, participate in the quiz and win SoC Development Board and  30000mAh Power Bank. We will be choosing a winner every day.


We invite you to join us at RISC-V 2021 for Lightning Talk: 

A System Level Verification and Validation Environment using SweRV

at Room 3004/3006 Visit:

Date: December 6, 2021
Time: 9:45 am – 9:55 am PST

Watch Recording









By NO Comment December 5, 2021

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