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Introduction to Automatic Register Verification

The Automatic Register Verification (ARV) is an add-on module to IDesignSpec suite. It is an application that provides the complete solution for implementing a register verification methodology. From creating a verification plan, to generating the stimulus sequences and coverage metrics, as well as creating SystemVerilog assertions, the Automatic Register Verification module automates all aspects of verifying registers.

The Automatic Register Verification (ARV) module works with IDS. It automatically generates the entire testbench, verification plan and Makefiles for complete register verification.

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It generates the Testbench components, Sequences, Verification Plans, Makefile to run simulation and XML containing results generated after automatically collecting data from the vendor simulation database. Popular specification standards such as IP-XACT, System RDL, CSV’s has been grown to such an extent to automatically generate any number of Register Model, RTL, Firmware , and Verification Code . The whole verification process can be further upgraded by automating code for formally verifying IP’s with slave interface, since it helps in reducing simulation efforts and the overheads involved in creating and maintaining block/chip level test-benches. Even though by using directed and constrained random test-cases we may miss out corner cases, which can only be verified formally.

In IDesignSpec formal verification can be done by extracting a list of properties from specification, each property describing a feature or a property. These properties are further used in formal tools to verify whether they are compliant with the RTL or not.

From the specifications point of view, we have an address space having registers at known addresses and bus interface used in communicating with those registers. These registers can be formally verified with the bus interface only if target location or the register or field where the response to the bus transaction is taking place. So for formally verifying an IP we need to know two things, i.e., Bus (Protocol), Register /Field (where there is response to the bus transaction)

Event Info:
Date :  26 Mar 2020,
Time Slot 1: 03:00 PM-04:00 PM CET
Time Slot 2: 11:00 AM-12:00 PM PDT

Presenter: Sakshi Saxena, Agnisys R&D Engineer

 

By March 26, 2020

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