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RECORDED WEBINAR: Introduction to SystemRDL (Part 1)
Presented by: Nikita Gulliya, Agnisys R&D Engineer
SystemRDL 2.0 Register Description Language is the industry standard from Accellera used for describing control/status registers and memories in circuit designs. SystemRDL human-readable descriptions are used as input to software tools for generating RTL, UVM register model, C/C++ Headers and documentation.  Its industry adoption continues to increase because it employs a golden-spec methodology that ensures synchronization of all register design, verification and documentation files from a single source.

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Click Here to view part 2 of the SystemRDL webinar series

In this webinar, we will provide an introduction to SystemRDL. We will provide working examples for describing basic registers and special registers such as Lock and Shadow.  We will show how to build a hierarchical spec for SoCs with parameterization features. We will also show how you can use IDesignSpec™ when SystemRDL is used as main input files for generating design and firmware header files.


  • SystemRDL Purpose
  • Structural Component Types
  • Data Types and Expressions
  • IP-XACT vs SystemRDL
  • SystemRDL 1.0 vs SystemRDL 2.0
  • SystemRDL for Register Design – Examples
    • Describing basic registers and special registers (Lock and Shadow)
    • Using signals, enum/structs
    • Interfacing to external memories
    • Building a hierarchical SystemRDL spec
    • Parameterization
    • SystemRDL as input to IDesignSpec and generated outputs (RTL and C Headers)
  • Q&A

This webinar will be useful for:

    • Hardware Designers
    • Verification Engineers
    • Firmware Engineers
    • Emulation Engineers
    • System Developers
    • IP developers
    • SoC developers
    • Managers or Directors
By NO Comment November 7, 2019

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