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LIVE WEBINAR: Introduction to SystemRDL (Part 2)
Presented by: Nikita Gulliya and Amanjyot Kaur, Agnisys R&D Engineers
SystemRDL 2.0 Register Description Language is the industry standard from Accellera used for describing control/status registers and memories in circuit designs. SystemRDL human-readable descriptions are used as input to software tools for generating RTL, UVM register model, C/C++ Headers and documentation.  Its industry adoption continues to increase because it employs a golden-spec methodology that ensures synchronization of all register design, verification and documentation files from a single source.
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In this webinar, we will go over a few SystemRDL UDPs and their use cases for RTL, UVM and C Headers. We will show working examples how you can describe UVM coverage, constraints and hdl_path.  We will also show how you can use IDesignSpec™ when SystemRDL is used as main input files for generating verification and documentation files.

Agenda:

  • SystemRDL User-Defined-Properties
    • RTL and Special Registers
    • UVM
    • C Header
  • SystemRDL for Verification (Examples)
    • Describing coverage and constraints
    • Hdl_path
  • SystemRDL as input to IDesignSpec and generated outputs (UVM and documentation)
  • Q&A

This webinar will be useful for:

    • Hardware Designers
    • Verification Engineers
    • Firmware Engineers
    • Emulation Engineers
    • System Developers
    • IP developers
    • SoC developers
    • Managers or Directors
By November 21, 2019

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