WEBINAR: Introduction to SystemRDL (Part 2) | Agnisys

SystemRDL 2.0 Register Description Language is the industry standard from Accellera used for describing control/status registers and memories in circuit designs. SystemRDL human-readable descriptions are used as input to software tools for generating RTL, UVM register model, C/C++ Headers and documentation.  Its industry adoption continues to increase because it employs a golden-spec methodology that ensures synchronization of all register design, verification and documentation files from a single source.

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In this webinar, we will go over a few SystemRDL UDPs and their use cases for RTL, UVM and C Headers. We will show working examples how you can describe UVM coverage, constraints and hdl_path.  We will also show how you can use IDesignSpec™ when SystemRDL is used as main input files for generating verification and documentation files.