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RECORDED WEBINAR: Register Verification – Tips and Tricks in IDesignSpec™
Presented by: Amanjyot Kaur, Agnisys R&D Engineer
IDesignSpec has become the de-facto solution for register design/verification. It has helped in the industry minimize SoC functional flaws that show up due to changes and errors in the functional specification by employing a golden specification methodology. IDesignSpec offers a wide-range of features and capabilities for various verification use cases and strategies. As requested by many of our users, in this webinar, we will show you several verification strategies and tips/tricks used by power-users of IDesignSpec.

This event has passed. To download slides and view recorded webinar, please fill the form below.


    • Tool Overview
    • Basic tests available in UVM RAL
    • Tips and Tricks
      • Advanced tests available in IDesignSpec
      • Setting UVM Coverage at block, register and field level
      • Defining UVM HDL_PATH for custom RTL
      • Widely-used UVM Properties
      • Enabling vertical reuse
    • Q & A

This webinar will be useful for:

    • Hardware Designers
    • Verification Engineers
    • Firmware Engineers
    • Emulation Engineers
    • System Developers
    • IP developers
    • SoC developers
    • Managers or Directors
By NO Comment October 10, 2019

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