Scheduled Webinar Details
We are bringing to you a series of webinars to go over technology that IP/FPGA/ASIC developers will find useful. We will also discuss the latest innovations in our tools. Click on any registration button below to sign-up for one or more free webinars.
- Webinar: Correct by construction SV UVM code with DVinsight – a smart editor Watch RecordingDate: 8-April-2020, Time: 10:00 AM-11:00 AM PDT
Presenter: Devender Pal Khari
Description: This webinar illustrates how the DVinsight (DVi) smart editor can help beginners as well as experienced DV engineers. It not only helps to shorten the learning curve of new DV engineers but also helps in accelerating error-free code development for expert DV professionals. DVi saves a lot of time and hassles in writing verification code by providing guidance to the user, because of its early warning system and ability to help the user to visualize the code. The DVi editor checker provides helpful insight into user code and ensures compliance with UVM best practices while adhering to established standards.There are hundreds of rules that a DV engineer must follow when creating a testbench infrastructure that conforms to UVM. If these rules are not adhered to, problems are not discovered until later in the verification process where they are more costly to correct because compilers do not catch UVM rules-based errors. DVi helps semiconductor organizations save huge costs as it understands the engineer’s intentions with uncanny accuracy and identifies issues quickly, during DV code creation, before they become problematic and lead to major debug challenges.
- Webinar: Creating portable UVM sequences with ISequenceSpec Watch Recording
Date : 9-April-2020, Time: 10:00 AM-11:00 AM PDT
Presenter : Amanjyot Kaur
Description: In functional verification, sequences play a vital role in verifying that the logic design abides by the specification. These stimuli are further translated by the drivers into the actual inputs of the design under verification.Overcoming the lack of a common set of sequences that can be shared across the teams, ISequenceSpec (ISS) enables users to describe the programming and test sequences of a device and automatically generate sequences, which can be used from an early design and verification stage to post silicon validation. ISS helps design, verification and validation teams to generate the unified test and programming sequences for various platforms, including SV, UVM, firmware, Tcl, etc. from a single specification.
- Webinar: Register automation from SystemRDL to PSS – Basic to Pro Watch Recording
Date : 16-April-2020, Time: 10:00 AM-11:00 AM PDT
Presenter : Nikita Gulliya
Description: This webinar teaches a methodology to easily define the HSI using SystemRDL and generate the desired code for different teams. Attendees will also learn how to leverage custom implementation sequences to create high level test scenarios in PSS to ensure the same sequences are being used by different teams across different platforms, thereby accelerating the verification cycle.
-Overview of SystemRDL including version 2.0 and its benefits-Modeling different types of registers using SystemRDL
-Generating different types of outputs such as RTL code, SystemC, C headers and documentation from a golden specification and customized to your requirements
-Generating a UVM based verification environment and standard tests to verify the HSI
-Creating custom sequences as building blocks for the high level test scenarios defined in PSS
- Webinar: Cross platform specification to code generation for IP/SoC with IDS-NG Watch Recording
Date : 23-April-2020, Time: 10:00 AM-11:00 AM PDT
Presenter : Azharuddin Saifi
Description : IDesignSpec NextGen (IDS NG) is a multi-platform product that helps users to create SoC specifications at the next generation level. It handles individual IP to sub-system compatible with Word, Excel, IP-XACT, RALF, CSV and System RDL. It generates design and verification code for registers and sequences in one integrated environment. IDS NG is the next generation of register and sequence specification tool that provides a one-stop-shop or a single tool that enables users to create every aspect of an executable register, field-parameter and sequence specification.
- Webinar: Advanced UVM RAL – callbacks, auto-mirroring, coverage model, and more Watch Recording
Date : 30-April-2020, Time: 10:00 AM-11:00 AM PDT
Presenter : Nitin Chaudhary
Description : The verification of large or complex designs targeted at ASIC/FPGAs is time consuming. However, with a good testbench architecture the workload can be greatly reduced.The UVM register layer classes are used to create a high-level, object-oriented model for memory-mapped registers and memories in a design under verification (DUV).An IDesignSpec (IDS) register model is an instance of a register block, which may contain any number of registers, register files, memories, and other blocks. Each register file contains any number of registers and other register files. Each register contains any number of fields, which mirror the values of the corresponding elements in hardware. Likewise, IDS can generate Register Callbacks, Register Arrays, Memories, Indirect Access Registers, FIFO Registers, Alias Registers, Interrupt Registers, Lock Registers and Coverage Models that are supported by the UVM register model in its UVM output.This webinar will discuss advanced constructs in UVM RAL and how IDS can be used to automatically generate them.
- Webinar: Functional safety and security in embedded systems Watch Recording
Date : 7-May-2020, Time: 10:00 AM-11:00 AM PDT
Presenter : Divya Chawla
Description : Functional Safety is the measure of the device behaviour depending on the protection occuring correctly in response to its input or failure in a predictable manner. Human errors, environmental stress and hardware failures should be handled properly if they occur in a design. This can done by having parity, Secded, CRC and ECC in the design.This webinar will outline various ideas and techniques to have a secure design with protection against failures/errors.
- Webinar: IP generators – the next wave of design creation Watch Recording
Date : 14-May-2020, Time: 10:00 AM-11:00 AM PDT
Presenter : Amanjyot Kaur
Description : In any System-on-Chip (SoC) design there are certain standard IPs that are ubiquitous and are used across all designs. A designer has two alternatives – either to spend time creating these IPs from scratch to meet their custom requirements or get them off-the-shelf. SLIP-G from Agnisys offers configurable standard IP generators as an extension to its Addressable Register generator tool. These IPs are designed to be easily customizable and configurable to meet any SoC requirements. Agnisys provides IPs such as GPIO, TIMER, I2C Master and PIC, which can also be configured and customized as per user’s need.This webinar will show how IP generators are a better way of creating customizable and configurable designs.
- Webinar: A flexible and customizable flow for IP connectivity and SoC design assembly Watch Recording
Date : 21-May-2020, Time: 10:00 AM-11:00 AM PDT
Presenter : Devender Pal Khari
Description : This webinar demonstrates a flexible and customizable flow for smart design assembly to meet specific design requirements. Flexible means support for IPs in different formats such as IP-XACT, RTL, Syste RDL, OpenOffice, Word, Excel, etc. Customizable means supporting fully parameterized configuration. Smart design assembly uses component generators that can not only generate the IPs but also the components such as aggregators, bridges, channels, bus fabrics, muxes, etc. wherever needed. This webinar highlights the following benefits of the flow for every SoC design and verification team:- Saves large amount of time by automation through text-based APIs- Flexibility to abstract ports to efficiently capture connections
– Ability to easily specify tie-offs, intentional opens and other special cases, where needed
– Support for built in Design Rule Checks to validate design connectivity before generating RTL
– Flexibility to add custom DRC checks.
- Webinar: Steps to setup RISC-V based SOC Verification Environment Watch Recording
Date : 28-May-2020, Time: 10:00 AM-11:00 AM PDT
Presenter : Anmol Rana
Description : IP verification is done at the block level focusing on its functionality. At the SoC level several types of bugs can be identified, including inter-block connectivity, data routing, interrupt handling and overall functionality. These require an SoC level verification environment where the CPU is also part of the simulation and the stimulus is written in C.This webinar discusses the steps to set up an SoC verification environment using RISC-V (SweRV design). The RISC-V tool chain will be introduced and used on a sample test case using compiler, assemble, linker for C and syncing with the SV_UVM counterpart.
- Webinar: Automatic verification using Specta-AV – a boost to verification productivity Watch Recording
Date : 04-June-2020, Time: 10:00 AM-11:00 AM PDT
Presenter : Nikhil Arora
Description: With the increasing complexity in IP design, verification effort takes 70% of the total development time. From creating a verification environment, test sequences and configurations to plumbing all the bits and pieces, a lot of manual steps are required. And because it is manual, it is fraught with danger of bugs, tedious and not a good use of time.Specta-AV is a comprehensive UVM Testbench Generator for IPs/SOCs. This tool automates verification using an industry-proven code generation technology. With the ability to parse hierarchical register specification from IP-XACT, System RDL, Word or Excel, and the ability to retarget complex sequences into various modelling languages such as System Verilog, Specta-AV facilitates a methodology where multiple SoC groups can align and work from a golden specification for autogenerating UVM Tests/Environments/Agents.This webinar will show how Specta-AV provides the best framework to generate a complete UVM testbench including sequence items, configurations, checkers, coverage and even the plumbing within UVM automatically.
- Webinar: AI based sequence detection for verification and validation of IP/SoCs Watch Recording
Date :11-June-2020, Time: 10:00 AM-11:00 AM PDT
Presenter : Asif Ahmad
Description :When writing a functional specification of a device, the designer captures the details of the programming sequences in normal English language. This must be converted into code by a human. With the recent advent of AI techniques, it is now possible to capture these sequences from natural/communication language and convert them into usable code.This webinar focuses on capturing verification and validation sequences by automatically generating them using the AI based sequence detection and then using those sequences in C/UVM verification code.
- Webinar: Understanding clock domain crossings Watch Recording
Date : 18-June-2020, Time: 10:00 AM-11:00 AM PDT
Presenter : Abhishek Bora Description :Various IP blocks within an SoC are often required to work in different asynchronous clock domains in order to satisfy the power constraints. Often, a metastability condition occurs which can lead to some consequences such as corrupted or lost data.This webinar will revolve around the various techniques used to avoid metastability as signals cross from one clock domain to another and how these are handled in IDesignSpec..