AI based sequence detection for verification and validation of IP/SoCs

AI based sequence detection for verification and validation of IP/SoCs

Understanding clock domain
crossings

Understanding clock domain crossings

A flexible and customizable flow for IP connectivity and SoC design assembly

A flexible and customizable flow for IP connectivity and SoC design assembly

Steps to setup RISC-V based SOC Verification Environment

Steps to setup RISC-V based SOC Verification Environment

Automatic verification using Specta-AV – a boost to verification productivity

Automatic verification using Specta-AV - a boost to verification productivity

Advanced UVM RAL – callbacks, auto-mirroring, coverage model, and more

Advanced UVM RAL – callbacks, auto-mirroring, coverage model, and more

Functional safety and security in embedded

systems

Functional safety and security in embedded systems

IP generators –
the next wave of design creation

IP generators – the next wave of design creation

Creating portable UVM sequences with ISequenceSpec

Creating portable UVM sequences with ISequenceSpec

Register automation from SystemRDL to PSS – Basic to Pro

Register automation from SystemRDL to PSS – Basic to Pro

Cross platform specification to code generation for IP/SoC with IDS-NG

Cross platform specification to code generation for IP/SoC with IDS-NG

Introduction to SystemRDL

(Part 2)

Recorded Webinar-Introduction to SystemRDL Part-2

Introduction to Automatic Register Verification (ARV)

Introduction to Automatic Register Verification (ARV)

Correct by construction SV UVM code with DVinsight -a smart editor

Correct by construction SV UVM code with DVinsight - a smart editor

Introduction to SystemRDL

(Part 1)

Recorded Webinar-Introduction to SystemRDL Part-1

Register Verification – Tips and Tricks in IDesignSpecRegister Verification Tips and Tricks in IDesignSpec

Register Design –
Tips and Tricks in IDesignSpecRecorded Webinar Register Design Tips Tricks IDesignSpec

Registers and Sequences: Design/Verification Best-Practices for Vertical ReuseRecorded Webinar Registers and Sequences

Generate Portable Sequences from
a Golden SpecificationGenerate Portable Sequences from a Golden Specification

5 Special Registers Useful for Today’s SoCs – Use Cases, Examples & UVM VerificationRecorded Webinar 5 Special Registers Useful for Todays SoCs

Hardware/Software Interface
(HSI) SpecificationRecorded Webinar Hardware Software interface HSI

Anupam Bakshi at DAC 2018
EDA Cafe

Fish Fry with Amelia Dalton
at DAC 2018

Auto-generate Implementation-level Sequences for Portable Stimulus Tools

Agnisys Inc. – Leading Electronic Design Automation (EDA)

DVInsight-Pro – Design Verification Editor Checker for SV/UVM

Verifying Registers using UVM
and IDesignSpec

How to create parameterized specification for semiconductor IP Design

Automatically Generate UVM Code From A Specification w/ IDesignSpec

Chalk Talk with EE Journal

EDA Cafe – DAC 2015