Using Machine Learning in Register Automation and Verification

Machine Learning (ML) is a powerful concept where the trainable engine and a dataset can be made to predict future outputs. This concept has been leveraged to help users create IP and SoC specification. The ML algorithms have been embedded in software that is not visible to the end user, which makes the creation of the register specification a simple and less erroneous task.

20 Advantages for Automating your ASIC or FPGA Transition from Specification to Design

The transition from specification to hardware is a challenging and time-consuming task in the design of complex ASIC and FPGA systems. Registers and memory-maps being an essential component of ASIC/FPGA designs, need to be managed and configured diligently, in order to avoid the potential errors, thereby improving the design quality and reducing the development time and cost.

15 Benefits of Working with Agnisys on your Chip Design Project

Semiconductor design is challenging during the best of situations. The amount of code that design teams must create and the complexity of the IP blocks that they must integrate makes their projects very difficult and the risks of success are significant. In order to manage these risks, project teams should gain the benefit of a partner with the products and services to help them succeed.

Designing IP and Device Driver for RISC-V

Developing and integrating IPs and device drivers with processor cores based on RISC-V is a daunting task that requires a lot of automation and expertise. In this presentation, we will discuss best-practices for design/verification of control/status registers (CSR) using template-based methodology. The design, firmware and verification teams can generate RTL, C/C++ Headers, UVM register model, Python and PDF from a golden specification.

In pursuit of Faster Register Abstract Layer (RAL) Model

RAL is used to model the registers and memories present in the design. UVM comes with a register package which is used to model these registers and memories. With its numerous advantages, there are also some disadvantages. The UVM RAL model is good for small testbenches but when one moves to large system level testbench which contains thousands of registers, it impacts the performance and adds significant load to the simulator designs.

How to automate a complete register verification environment

Memory mapped registers provide reconfigurability and control to an Intellectual Property Block (IP) or System on Chip designs (SoC) and are essential to the development of hardware systems. The sheer number of register bits, their access types, properties and the functionality which they control can be staggering in modern designs.

How to Streamline Universal Verification Methodology Process

The increasing prevalence of electronic systems results in complexly that make designing such integrated circuits challenging, but also turns the verification process into a rigorous and time-consuming step. Originally, verification of the integrated circuit used to be performed manually, however with the exponential growth rate of the circuit’s complexity the process needed to be automated and streamlined as much as possible.

Client Engagement Snapshot

Allegro Selects Agnisys IDesignSpec™ and ARV-Sim™ for Specification Creation, Automatic HDL and UVM Model Generation for Register and Memory Blocks

CERN Selects Agnisys IDesignSpec for The TOTEM Experiment Project at the
Large Hadron Collider

Discretix using IDesignSpec™

Xingtera using IDesignSpec