RAL is used to model the registers and memories present in the design. UVM
comes with register package which is used to model these registers and
memories. With its numerous advantages, there are also some disadvantages.
The UVM RAL model is good for small testbenches but when one moves to
large system level testbench which contains thousands of registers, it impacts
the performance and adds significant load to the simulator. To overcome
these performance issues, we have developed and benchmarked several
alternative RAL models. The underlying approach in the first two models (SV
RAL with lookup and C based RAL with lookup) is to optimize the number
of handles to register or field classes and to store register information in
associative-array based lookup tables. There is also a third model which uses
the register and field classes written in C++ instead of “uvm_reg” and
“uvm_reg_field” classes.

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