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Newsletter 2021 Q2 | Agnisys

Various new enhancements have been introduced recently in products like IDesignSpec™ (IDS), IDS NextGen™, and ISequenceSpec™ (ISS). Significant new enhancements to IDS are Multicast/Broadcast Address Decoder, parameterization update of software access of field, and creating read-write (RW) pairs of fields. ISS has been enhanced with read/write on hardware interface and memory, and a very robust mechanism for Git integration is provided in IDS NextGen.

Parameterization is one of the ways by which users can configure the software access of the field at elaboration time. Another very important addition in IDS has been the introduction of rwpair fields where two separate fields residing at the same offset have different accesses. Moreover, IDS also supports hierarchical decoding/accessing of slave IPs in a multicast/broadcast manner for software write transactions.

Talking about ISS, verification engineers can now have a breath of relief as Agnisys introduces the concept of read/write on hardware interface and memory. So, now engineers need not spend a huge amount of time verifying the design. This new feature comes in very handy since users can use these additional constructs and create a sequence to help in verification of IPs.

In IDS NextGen, by using Git integration, users can differentiate two IDS-NG input files using Git and can show the diffs in GUI format. Users can also discard their changes from Origin or Head. Moreover, cloning repositories, creating and managing  branches, committing changes, pulling from the origin, and pushing to the origin can also be done from the tool itself.

As always, your comments and suggestions are welcome.

Register Field Access Update At Elaboration Time: IDesignSpec™ supports a variety of software accesses for defining field bits of a register component. The register bits (fields) can be accessed by the register bus based on the defined access for software read/write transactions. Although the software accesses are generally defined while capturing the register definition itself as static attributes, IDS has been enhanced to support overriding of these accesses at the elaboration time using parameters. Read More

Read/Write on HW Interface and Memory in ISS: With the growing complexity of the chip, design/verification engineers spend a hefty amount of time verifying the functionality with many tedious scenarios. While reading/writing design registers with programming/test sequences is a common methodology, often there is a need to write data on some hardware pin or check/read a value from a hardware pin. For example, it is a very common scenario to wait and check for an interrupt signal from a design to get high and then perform some operation. Read More

Multicast/Broadcast Address Decoder: There are three ways to decode addresses for the IP blocks. One is the absolute decoding, where all address bits are decoded at each block. This is the default flow. The second way is to do hierarchical decoding in which the address bits are divided into two parts: the MSB part is used to decode the block address and the LSB part is used to decode the register being addressed once the block address (the MSB part) is selected. The third way is to map a slave select to certain address bits in the bus (say, APB) interface thus, providing a special decoder after any bridge (say, AHB-APB) that users will have in their system allowing multicasting/broadcasting while accessing the slaves. Read More

Git Integration in IDS-NG: Git is a fast distributed revision control system for tracking changes in a set of files using repositories, and branches. Its goals include speed, data integrity, and support for distributed, non-linear workflows. Read More

“rwpair” at Field Level: Registers are a basic building block of the register space. Each bit or set of bits within the register controls some behavior of the circuit, and is known as a field. Every field has at least two accesses: software (SW) access and hardware (HW) access. The SW access is the access from the host register bus, e.g., AMBA or I2C, and the HW access is the access to the register from the user defined hardware logic. Read More