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The 5 Ways Register Generation Tools Reduce SV/UVM Implementation Time

The 5 Ways Register Generation Tools Reduce SV/UVM Implementation Time

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Modern SoCs get more and more complicated each and every day.  As the complexity of modern electronic semiconductor device design increases, niche tools for every nook and cranny of the design process emerge to help semiconductor companies keep pace with their emerging challenge.  Register and memory map definition and code generation is one example of a niche tool that has become mainstream. 

The reason why these register generation tools have been adopted and the rate of adoption is increasing is because there are so many benefits of doing so.  There are few opportunities where a single tool can provide benefits to multiple groups.  Project leaders should consider embracing a modern register and memory map generation tool to keep up with the complexities of design, verification and embedded coding. 

register generation tools flow

These 5 ways, are just the start of why it makes sense to adopt register generation tools:

  1. These tools start with a simple input format specification created by the architect or senior design engineers.  The tool takes that specification and expands it to provide multiple teams with functionally correct, synthesizable RTL code, UVM verification code, C-Header files and documentation.  
  2. One group that is always under the gun is the Design Verification team.  As the specification is completed, the DV team uses the code generated to accelerate creation of the UVM register abstraction model.   Doing it this way provides the design verification team with instant access to an up-to-date RTL model and updated test-bench related code. The DV team is no longer working with a old design code that is out of date, or discover at a later time that changes in the design were not reflected in the testbench resulting in bugs or incomplete tests.
  3. These tools provide functionality not available in old or technology specific formats such as SystemRDL, IP-XACT, or simple spreadsheet methods.  These tools take the specification and produce complete and robust code for each stakeholder.  Additionally, the tools are configurable to enable the customization of target outputs that may be specific to your company.
  4. Tools like this enable fast turn-around times, allowing multiple iterations per day.  Issues discovered during design verification that require a specification changes commonly drive these iterations.  With tools like these, enable the resulting specification change to immediately propagate to each group that is a consumer of the impacted code change. 
  5. Because these tools are tested against many designs, the resulting code that is generated is both syntactically and semantically correct.  This eliminates yet another error source for design, verification and firmware teams. 

The bottom line about register generation tools and SV/UVM implementation time:

By adopting an automatic code generation tool for registers and memory maps from specifications, semiconductor design teams gain significant productivity benefits, reduce the risk of complex designs while removing multiple error sources that emerge as design specifications change. 

20 advantages for automating your ASIC or FPGA transition from Specification to Design

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