Agnisys to Showcase Expertise at DVCon US with Exclusive Short Workshop and Tutorial Sessions
BOSTON, Mass. (01 March 2024) Agnisys, Inc., the pioneer and industry leader in Executable Golden Specification Solutions™ is thrilled to announce […]
Events
Electronic Design Automation Trade Show Update – 52DAC
Overheard a lot of talk about “Shift Left” – which refers to the higher levels of abstraction leading to higher
A Quick Look Back at a Virtual DAC
In my last blog post, I talked a bit about the history of the annual Design Automation Conference (DAC) and
Efficient Design Automation Solutions: Meeting Industry Demands for Optimal Efficiency
The electronics industry’s current state intensifies demands on design, verification, and validation teams, requiring them to achieve more with fewer
2015 Year End review – DV Challenges
Wow, what a marvelous year 2015 has been to Agnisys, full of events at the various technical exhibitions, new customers,
Semiconductor Register Specification: Shadow of a Shadow
So we have been working in the register specification space for a long time. We came out with the IDesignSpec
Does UVM sometimes make you feel stupid?
Somewhere in the deep trenches of a UVM-based verification project, an engineer teeters on the verge of insanity.
Creating Test Sequences for RISC-V Cores and SoCs
By Louie De Luna, Agnisys Chief Product Evangelist
Setting the Stage for the Next Abstraction
By Louie De Luna, Agnisys Chief Product Evangelist
Making Way For Register Specification Software
While more registers mean more functionality and configurability, more is not always better.
Agnisys makes Design Verification process extremely efficient!
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry.
Not your Average UVM Testbench Generator – Unveiling at DAC 2019
By Louie De Luna, Agnisys Chief Product Evangelist
Agnisys to Unveil Specta-AV at DAC 2019
BOSTON, MA – May 20, 2019 – Agnisys, Inc. to unveil Specta-AV™, a comprehensive UVM Testbench Generator for today’s IPs/SoCs,
Out of the Office – Lessons from a client visit in Edinburgh
As we travel professionally, sometimes we tend to miss some of the scenery along the way. We can get a
Automatic Register Verification Gains Acceptance at DAC
With the Design Automation Conference wrapping up this week in San Francisco, there is one thing we can say
Getting Ready for DVCon India 2014
It is penultimate day – the day before the big event! Preparing and launching the first ever DVCon India event
The Ultimate Shift Left
Important observations from Einstein and New England’s ice traders..
Musings from ARM TechCon Santa Clara 2015
The first day for exhibitors had lots of foot-traffic. Mostly casual onlookers, but a few who were genuinely interested in
In preparation for DAC 2014
As an EDA company our development cycle seems to revolve around DVCon and DAC. This year DVCon and DAC
Age of cooperation, is it?
Its heartening to see greater cooperation between various EDA companies, both big and small. The ongoing work under Accellera for
DAC Day 2: System On Chip Design Challenges Addressed by Agnisys
System on Chip Design Challenges – The Highlight of DAC Day 2 It was a very busy day for Agnisys
Adopting New Methods For Faster Development Of RISC-V based SoCs
The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course,
EDA Companies must Collaborate or Die
Recently at the sidelines of DAC, Anupam Bakshi, CEO of Agnisys, Inc. sat down with Karen Bartleson, Director of
DVCon Europe Needs Automatic Register Verification and Generation
I feel like a bumblebee, going from the DVCon in US, to the next one in India to then
DVCon India takes off!
DVCon had a solid start in Bangaluru, India. The audited attendee numbers will be coming in later, but we believe
IDesignSpec Provides Complete Register Design Automation
Published on 05-19-2013 07:30 PM in Semiwiki
Repurposing von Neumann Architecture with SRAM-based Register File
By Louie De Luna, Agnisys Chief Product Evangelist
Register Automation using Machine Learning
By Louie De Luna, Agnisys Director of Sales and Marketing
DVinsight: Universal Verification Methodology IDE at DAC Day 3
Ending the last day of DAC strong with a presentation of DVinsight, a Universal Verification Methodology IDE The highlight of
News
Agnisys Demonstrates Solutions For RISC-V System Development
Milpitas, Calif., December 04, 2019 – Agnisys, Inc., will present its customer proven SoC design and intellectual property (IP) solutions
News
Agnisys Presents ISequenceSpec Sequence Generator at DVCon India 2019
Bangalore, India – September 11, 2019 – Agnisys, Inc., the leading EDA provider of the industry’s most comprehensive solution for
News
Agnisys Showcases Test Sequence Generator at DVCon Europe
Munich, Germany – October 21, 2019 – Agnisys, Inc., the leading EDA provider of the industry’s most comprehensive solution for Design
News
Agnisys Announces Three New Design and Verification Flow Products
Three new products generate IP, assemble complete chips, and provide a common front end for SoC automation BOSTON, Mass. –
Using IVerifySpec to test IDesignSpec
IDesignSpec generates several outputs from a single spec. We started out as a simple tool that just dealt with registers.
DAC Day 1: Universal Verification Methodology Adoption
The first day of the Design Automation Conference for Agnisys was exciting. We experienced a higher traffic flow than Monday
EDA Is Advancing – but Where Are the Women?
1981 marked the beginning of EDA as an industry. Within a few years there were many companies specializing in EDA,
Customer’s Music and DVCon 2012
I admit it, I get a high when meeting customers and hearing how they are using our tools. It is
