IDesignSpec is now on Xuropa
Lowell, MA, June 10th, 2010 IDesignSpec is now available for trial on Xuropa. This will enable trial of the software […]
Agnisys announces DVCon specials for IDesignSpec™
Lowell, MA. Feb 28, 2014 – Agnisys, Inc. today announced two special offers at the start of DVCon 2014. (1)
Agnisys announces ‘Mystic Tool’ at DVCon 2014
Lowell, MA. Feb 28th, 2014 — Agnisys Inc. today announced that it is all set to introduce a new tool code
Agnisys Automates Development of ARM-Based Designs
With the growing requirement for configurable IP, processor and SoC, the number of registers, access type and interrupts have gone
Agnisys Expands Product Portfolio With Portable Sequence Generator
ISequenceSpec Automatically Generates Sequence for Verification, Firmware Validation Used From Early Design Through Post-Silicon Validation LOWELL, MA–(Marketwired – May 24,
Customer’s Music and DVCon 2012
I admit it, I get a high when meeting customers and hearing how they are using our tools. It is
5 tips to speed up regressions
Hardware design verification consumes more than 60% of resources, often more than that. These resources are not just engineers but
What is Collaborative Specification?
It’s been quite a while since I talked with Agnisys CEO and founder Anupam Bakshi, when he described their successful first user
ISO 26262: Feeling Safe in Your Self-Driving Car
The word “safety” can mean a lot of different things to different people, but it’s a word we hear frequently
Agnisys Offers DVInsight – A SystemVerilog – Universal Verification Methodology IDE | Agnisys
San Francisco, CA. June 2nd, 2014 – Agnisys, Inc. Launches DVInsight™, an Integrated Development Environment (IDE) for creating SystemVerilog (SV)
Newsletter 2022 Q4
There are a great number of improvements in Agnisys tools. The primary new enhancements include flopped interrupt support in RTL,
A Unified Development Flow for Embedded Systems
When engineers discuss system-on-chip (SoC) designs, they’re almost always talking about embedded systems with both hardware and software content. In
Newsletter 2022 Q3 | Agnisys
Agnisys tools have a remarkable set of enhancements. The major new enhancements include plugin environment support in IDS-NG™, expression support
Newletter 2022 Q2 | Agnisys
Agnisys tools have an amazing set of enhancements. The major new enhancements include Formal Verification through ARV-Formal™, support of chip-inside-chip
Newsletter 2022 Q1 | Agnisys
In our first Newsletter of 2022 we are drawing your attention to new capabilities in the IDesignSpec family of products.
Newsletter Q1 2022
In our first Newsletter of 2022 we are drawing your attention to new capabilities in the IDesignSpec family of products.
Newsletter 2021 Q3 | Agnisys
Various new significant enhancements have been introduced recently in products such as IDesignSpec™ (IDS), IDS NextGen™ (IDS-NG), SLIP-G™, ASVV™, and
Newsletter 2021 Q2 | Agnisys
Various new enhancements have been introduced recently in products like IDesignSpec™ (IDS), IDS NextGen™, and ISequenceSpec™ (ISS). Significant new enhancements
Newsletter 2021 Q1 | Agnisys
Various new enhancements have been introduced recently in IDesignSpec™ (IDS). A significant new enhancement to IDS has been the introduction of
Newsletter 2020 Q4 | Agnisys
Happy New Year 2021 to you all !!! With the new year, Agnisys tools have an amazing set of enhancements.
Newsletter 2020 Q3 | Agnisys
Various new enhancements have been introduced recently in products like IDesignSpec™ (IDS) and ASVV™. A significant new enhancement to IDS
Newsletter 2020 Q2 | Agnisys
In this newsletter, you will find articles about the basic differences between Paged registers and Alternate register, Auto-Mirroring for volatile
Newsletter 2019 Q4 | Agnisys
This newsletter will give you a brief idea of various enhancements which have been made in Agnisys Tools and products.
Newsletter 2019 Q3 | Agnisys
In this newsletter, you will find thoughts and insights about SystemRDL loopholes, security design strategies in IDesignSpec, RISC-V TileLink Bus Protocol Support
Newsletter 2019 Q2 | Agnisys
In this newsletter, you will find articles about the basic differences between SystemRDL, YAML & RALF, overcoming challenges in writing
Newsletter 2019 Q1 | Agnisys
In this newsletter, you will find articles about the basic differences between IP-XACT and SystemRDL, best practices on how to
DVCon Europe Special Edition – Agnisys Spotlight 2018 | Agnisys
With DVCon Europe 2018 just around the corner, this special edition of the Agnisys Newsletter focuses its spotlight on the
DAC Special Edition – Agnisys Spotlight 2018 | Agnisys
A lot is happening at Agnisys this quarter. We are delighted to introduce this DAC Special Edition of the Agnisys
DVCon US 2018 Special Edition | Agnisys
With DVCon 2018 just around the corner, this special edition of the Agnisys Newsletter focuses its spotlight on the future.
Spotlight – 2017 Dec | Agnisys
Agnisys wishes you a joyful and prosperous 2018. We are delighted to introduce the last edition of the Agnisys Spotlight
Spotlight – 2017 Oct | Agnisys
Thank you for visiting October Agnisys Spotlight. In this issue, we review several enhancements in design specification using IDesignSpec –
Spotlight – 2017 June | Agnisys
Thank you for reading the June Agnisys Spotlight. In this issue, we review several enhancements in design specification using IDesignSpec.
Spotlight – 2017 Feb | Agnisys
Thanks for reading the first issue of the Newsletter for year 2017. As usual, this newsletter comes directly from the
Spotlight – 2016 Nov | Agnisys
We are happy to bring to you the 2nd issue of the Agnisys newsletter on schedule. This newsletter comes directly
Spotlight- 2016 Aug | Agnisys
In this world of uncertainty, engineers want guarantees in all aspects of System Development. To a large extend the sysdev
