Chip Development Shift Left Starts with the Specifications
American statesman Benjamin Franklin is famously quoted as saying “in this world, nothing is certain except death and taxes.” […]
Specification Automation
How Using Your Specification to Automate Code Generation Enforces Conformance to Product Requirements
Every IP and chip design is created for one reason: to build a successful electronic product. This is true regardless
Enhancing RTL Design: Alias Register Support with Lock Mechanism in RTL Design
Alias Registers in RTL Design: An alias register is a hardware feature that allows multiple names or addresses that refer
Empowering Designers: The User-Friendly World of IDesignSpec GUI Options
Introduction The IDesignSpec™ Suite by Agnisys stands as a versatile solution, simplifying the capture of hardware/software specifications in diverse formats
Too Many Iterations? How to Avoid Three Common Problems in Semiconductor Design
Developing semiconductor intellectual property (IP), system-on-chip (SoC) designs, and complete systems is enormously challenging. Even a small error in the
Six Smart Ways Specification Automation Reduces Register Implementation Time
Modern system-on-chip (SoC) devices get more and more complicated each and every day. As the size and complexity of modern electronic
Bridging the Gap: Agnisys Contribution to Specification Automation
Agnisys offers a leading solution with comprehensive features to guarantee the accuracy of each semiconductor component right from the beginning.
Agnisys: Pioneers in Specification Automation and Beyond
In the ever-accelerating landscape of technological advancement, Agnisys has emerged as a trailblazer, reshaping the electronic design automation (EDA) industry
Custom IP Design and AI-Based Verification
Introduction Engineers have consistently strived to expedite ASIC development. Our latest endeavor at Agnisys introduces automation that captures specifications in
Three Smart Steps to Quickly Test a Register Map for Your Entire SoC
As I noted in a recent post, registers appear everywhere in system-on-chip (SoC) design. Architecturally defined registers form the hardware-software
Electronic Design Automation Trade Show Update – 52DAC
Overheard a lot of talk about “Shift Left” – which refers to the higher levels of abstraction leading to higher
CERN Selects IDesignSpec for The TOTEM Project at the Hadron Collider
The Large Hadron Collider (LHC) at CERN is the worlds largest and most powerful particle accelerator. This research facility enables some
Top 2018 Agnisys Resources
Every year we take a look back at the resources we’ve created to determine what you’ve found most useful. We
#47DAC musings
We almost didn’t go to DAC this year, and that would have been a big mistake. Monday started out with
Begin Initialization Sequence – 10, 9, 8, …
OK rockets are not taking off yet, but we are excited to launch a new capability for our IDesignSpec suite
2015 Year End review – DV Challenges
Wow, what a marvelous year 2015 has been to Agnisys, full of events at the various technical exhibitions, new customers,
Semiconductor Register Specification: Shadow of a Shadow
So we have been working in the register specification space for a long time. We came out with the IDesignSpec
Does UVM sometimes make you feel stupid?
Somewhere in the deep trenches of a UVM-based verification project, an engineer teeters on the verge of insanity.
How to Improve Your IC Design and Reduce Errors with Automation Solutions from Agnisys
Has a chip ever been released that was entirely free of design errors? Not likely. While today’s design teams must
Setting the Stage for the Next Abstraction
By Louie De Luna, Agnisys Chief Product Evangelist
Making Way For Register Specification Software
While more registers mean more functionality and configurability, more is not always better.
How To Create Complex Registers in IDesignSpec
We talk about the creation of complex registers in IDesignSpec and the generation of their suitable RTL and UVM models.
Agnisys makes Design Verification process extremely efficient!
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry.
5 Ways Register Generation Tools Reduce SV/UVM Implementation Time
Modern SoCs get more and more complicated every day. As the complexity of modern electronic semiconductor device design increases, niche
Not your Average UVM Testbench Generator – Unveiling at DAC 2019
By Louie De Luna, Agnisys Chief Product Evangelist
Automating Register Verification with 100% Functional Coverage
By Louie de Luna, Agnisys Director of Sales and Marketing
Semiconductor Data Sheet Automation – Just The Way You Want It
Moore’s law prediction about the increase in density of an SoC design continues to prove accurate with each advancement of
What Every Engineer Should Know About SoC Register Generation
Register Generation is a Must-Have Capability Today’s SoC designs contain several thousands of registers and memory map elements. The design
Integration is Key for the Adoption of Specification Automation
I frequently delve into the solutions Agnisys offers for the seamless generation of design, SoC verification, testing, software, validation, and
Agnisys to Unveil Specta-AV at DAC 2019
BOSTON, MA – May 20, 2019 – Agnisys, Inc. to unveil Specta-AV™, a comprehensive UVM Testbench Generator for today’s IPs/SoCs,
Out of the Office – Lessons from a client visit in Edinburgh
As we travel professionally, sometimes we tend to miss some of the scenery along the way. We can get a
What’s New and What’s Next in Specification Automation?
Over the last few months, I’ve primarily shared two kinds of posts on this blog. The Design Automation Conference (DAC)
Getting Ready for DVCon India 2014
It is penultimate day – the day before the big event! Preparing and launching the first ever DVCon India event
The Ultimate Shift Left
Important observations from Einstein and New England’s ice traders..
Musings from ARM TechCon Santa Clara 2015
The first day for exhibitors had lots of foot-traffic. Mostly casual onlookers, but a few who were genuinely interested in
IDesignSpec: An Engineering tool with a difference.
I’m so excited … After years of work, my team and I have converted a word processor into an Engineering
Why is it difficult to make your first EDA tool sale?
As you know we have created a brand new EDA tool that saves people a lot of time and money.
Questa® VIP validates IDesignSpec generated IP
In our domain, we automatically generate registers and memory interface which can interface with all the standard bus protocols. If
Great turnout at the Design Automation Conference
We had a great first day at DAC. All the talk about recession and economic doom were hard to believe.
DAC Day 2: System On Chip Design Challenges Addressed by Agnisys
System on Chip Design Challenges – The Highlight of DAC Day 2 It was a very busy day for Agnisys
Is cheap EDA tool an oxymoron?
Business schools teach us that the way to set the price on a product has nothing to do with the
It’s All In The Sequence
Whether dealing with SoCs or a disaster in space, determining the correct set of steps is vital. No project
Adopting New Methods For Faster Development Of RISC-V based SoCs
The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course,
EDA Companies must Collaborate or Die
Recently at the sidelines of DAC, Anupam Bakshi, CEO of Agnisys, Inc. sat down with Karen Bartleson, Director of
DVCon Europe Needs Automatic Register Verification and Generation
I feel like a bumblebee, going from the DVCon in US, to the next one in India to then
DVCon India takes off!
DVCon had a solid start in Bangaluru, India. The audited attendee numbers will be coming in later, but we believe
IDesignSpec Provides Complete Register Design Automation
Published on 05-19-2013 07:30 PM in Semiwiki
What ARE the Root Causes of Functional Flaws?
By Louie de Luna, Agnisys Director of North American Sales and Marketing
First sale is always sweet!
I’m thrilled. Finally, we have a customer who sees the value that IDesignSpec brings for his company. We are indeed
Repurposing von Neumann Architecture with SRAM-based Register File
By Louie De Luna, Agnisys Chief Product Evangelist
Register Automation using Machine Learning
By Louie De Luna, Agnisys Director of Sales and Marketing
Agnisys Demonstrates Solutions For RISC-V System Development
Milpitas, Calif., December 04, 2019 – Agnisys, Inc., will present its customer proven SoC design and intellectual property (IP) solutions
Agnisys to Develop Next-Generation GDDR6 PHY IP for Six Semiconductor
BOSTON, MA – December 3, 2019 – Agnisys, Inc.® today announced that The Six Semiconductor Inc., an analog mixed-signal IP
FABU America Selects Agnisys to Create Executable Design Specification
BOSTON, MA – October 31, 2018 – Agnisys today announced that FABU America, Inc. has chosen its IDesignSpec™ software for creating
Agnisys Presents ISequenceSpec Sequence Generator at DVCon India 2019
Bangalore, India – September 11, 2019 – Agnisys, Inc., the leading EDA provider of the industry’s most comprehensive solution for
Agnisys Showcases Test Sequence Generator at DVCon Europe
Munich, Germany – October 21, 2019 – Agnisys, Inc., the leading EDA provider of the industry’s most comprehensive solution for Design
Agnisys Announces Three New Design and Verification Flow Products
Three new products generate IP, assemble complete chips, and provide a common front end for SoC automation BOSTON, Mass. –
Agnisys Announces Series of Webinars on Chip Specification Automation
Online events support remote learning, accommodating worldwide development teams with live sessions and on-demand replay BOSTON, Mass. – May 21,
Using IVerifySpec to test IDesignSpec
IDesignSpec generates several outputs from a single spec. We started out as a simple tool that just dealt with registers.
