Enhancing RTL Design: Alias Register Support with Lock Mechanism in RTL Design
Alias Registers in RTL Design: An alias register is a hardware feature that allows multiple names or addresses that refer […]
Alias Registers in RTL Design: An alias register is a hardware feature that allows multiple names or addresses that refer […]
Introduction The IDesignSpec™ Suite by Agnisys stands as a versatile solution, simplifying the capture of hardware/software specifications in diverse formats
Developing semiconductor intellectual property (IP), system-on-chip (SoC) designs, and complete systems is enormously challenging. Even a small error in the
Modern system-on-chip (SoC) devices get more and more complicated each and every day. As the size and complexity of modern electronic
Agnisys offers a leading solution with comprehensive features to guarantee the accuracy of each semiconductor component right from the beginning.
In the ever-accelerating landscape of technological advancement, Agnisys has emerged as a trailblazer, reshaping the electronic design automation (EDA) industry
Introduction Engineers have consistently strived to expedite ASIC development. Our latest endeavor at Agnisys introduces automation that captures specifications in
As I noted in a recent post, registers appear everywhere in system-on-chip (SoC) design. Architecturally defined registers form the hardware-software
Overheard a lot of talk about “Shift Left” – which refers to the higher levels of abstraction leading to higher
The Large Hadron Collider (LHC) at CERN is the worlds largest and most powerful particle accelerator. This research facility enables some
Every year we take a look back at the resources we’ve created to determine what you’ve found most useful. We
We almost didn’t go to DAC this year, and that would have been a big mistake. Monday started out with
OK rockets are not taking off yet, but we are excited to launch a new capability for our IDesignSpec suite
Wow, what a marvelous year 2015 has been to Agnisys, full of events at the various technical exhibitions, new customers,
So we have been working in the register specification space for a long time. We came out with the IDesignSpec
Somewhere in the deep trenches of a UVM-based verification project, an engineer teeters on the verge of insanity.
Has a chip ever been released that was entirely free of design errors? Not likely. While today’s design teams must
By Louie De Luna, Agnisys Chief Product Evangelist
While more registers mean more functionality and configurability, more is not always better.
We talk about the creation of complex registers in IDesignSpec and the generation of their suitable RTL and UVM models.
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry.
Modern SoCs get more and more complicated every day. As the complexity of modern electronic semiconductor device design increases, niche
By Louie De Luna, Agnisys Chief Product Evangelist
By Louie de Luna, Agnisys Director of Sales and Marketing
Moore’s law prediction about the increase in density of an SoC design continues to prove accurate with each advancement of
Register Generation is a Must-Have Capability Today’s SoC designs contain several thousands of registers and memory map elements. The design
I frequently delve into the solutions Agnisys offers for the seamless generation of design, SoC verification, testing, software, validation, and
BOSTON, MA – May 20, 2019 – Agnisys, Inc. to unveil Specta-AV™, a comprehensive UVM Testbench Generator for today’s IPs/SoCs,
As we travel professionally, sometimes we tend to miss some of the scenery along the way. We can get a
Over the last few months, I’ve primarily shared two kinds of posts on this blog. The Design Automation Conference (DAC)
It is penultimate day – the day before the big event! Preparing and launching the first ever DVCon India event
Important observations from Einstein and New England’s ice traders..
The first day for exhibitors had lots of foot-traffic. Mostly casual onlookers, but a few who were genuinely interested in
I’m so excited … After years of work, my team and I have converted a word processor into an Engineering
As you know we have created a brand new EDA tool that saves people a lot of time and money.
In our domain, we automatically generate registers and memory interface which can interface with all the standard bus protocols. If
We had a great first day at DAC. All the talk about recession and economic doom were hard to believe.
System on Chip Design Challenges – The Highlight of DAC Day 2 It was a very busy day for Agnisys
Business schools teach us that the way to set the price on a product has nothing to do with the
Whether dealing with SoCs or a disaster in space, determining the correct set of steps is vital. No project
The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course,
Recently at the sidelines of DAC, Anupam Bakshi, CEO of Agnisys, Inc. sat down with Karen Bartleson, Director of
I feel like a bumblebee, going from the DVCon in US, to the next one in India to then
DVCon had a solid start in Bangaluru, India. The audited attendee numbers will be coming in later, but we believe
Published on 05-19-2013 07:30 PM in Semiwiki
By Louie de Luna, Agnisys Director of North American Sales and Marketing
I’m thrilled. Finally, we have a customer who sees the value that IDesignSpec brings for his company. We are indeed
By Louie De Luna, Agnisys Chief Product Evangelist
By Louie De Luna, Agnisys Director of Sales and Marketing
Milpitas, Calif., December 04, 2019 – Agnisys, Inc., will present its customer proven SoC design and intellectual property (IP) solutions
BOSTON, MA – December 3, 2019 – Agnisys, Inc.® today announced that The Six Semiconductor Inc., an analog mixed-signal IP
BOSTON, MA – October 31, 2018 – Agnisys today announced that FABU America, Inc. has chosen its IDesignSpec™ software for creating
Bangalore, India – September 11, 2019 – Agnisys, Inc., the leading EDA provider of the industry’s most comprehensive solution for
Munich, Germany – October 21, 2019 – Agnisys, Inc., the leading EDA provider of the industry’s most comprehensive solution for Design
Three new products generate IP, assemble complete chips, and provide a common front end for SoC automation BOSTON, Mass. –
Online events support remote learning, accommodating worldwide development teams with live sessions and on-demand replay BOSTON, Mass. – May 21,
IDesignSpec generates several outputs from a single spec. We started out as a simple tool that just dealt with registers.